Generally, power semiconductor devices have been used as non-contact switches. Therefore, it has been required for the power semiconductor devices to produce lower losses therein. For reducing the losses produced therein, techniques for ON-state voltage lowering and switching loss reduction have been explored. It has been known to persons skilled in the art that there exists a tradeoff relationship between the ON-state voltage and the switching (turnoff) loss of power semiconductor devices. The tradeoff relation is called the “ON-state-voltage turnoff-power-loss tradeoff characteristics” for IGBT's and the “forward-voltage reverse-recovery-loss tradeoff characteristics” for PIN diodes.
These tradeoff characteristics are the indices of loss generation in the power devices that have required improvement. The ON-state-voltage turnoff-power-loss tradeoff characteristics and the soft switching performances are not simultaneously improved very often by the conventional methods known to persons skilled in the art. Therefore, it has been an important problem to improve both the ON-state-voltage turnoff-power-loss tradeoff characteristics and the soft switching performances at the same time. Since the turnoff-power-loss reduction is affected by the high-speed switching performances, it is very important to improve the high-speed switching performances and the soft switching performances at the same time.
The below-listed Patent Document 1 describes a technique for improving both the ON-state-voltage turnoff-power-loss tradeoff characteristics and the soft switching performances by an IGBT. The IGBT includes an n-type silicon layer between first and second major surfaces. The silicon layer includes an n-type region and a p-type region. The IGBT also includes a cathode formed of a first metal film arranged on the first major surface and an anode formed of a second metal film covering the second major surface. The IGBT is a power semiconductor device specifically for high reverse voltage use that includes, as described from the side of the second major surface, a p-type anode region, an n-type field stop layer in contact with the anode region and doped more heavily than the silicon layer, and the silicon layer in contact with the field stop layer. The field stop layer is doped with at least one kind of dopant having at least one donor level between the valence band edge and conduction band edge of silicon and the donor level is far from the conduction band edge of silicon by more than 200 meV. Patent Document 1 describes the use of sulfur and selenium as the dopant.
The below-listed Patent Document 2 proposes a technique for reducing the total losses consisting of a turnoff power loss and a steady state loss and for preventing oscillations from occurring on voltage and current waveforms. The technique disclosed in the Patent Document 2 forms an n+-type buffer region and a first n−-type drift region. The thickness of the first n−-type drift region and the impurity dose amount for forming the n+-type buffer region are determined so that the edge of the depletion layer expanding in the first n−-type drift region, when a rated voltage is applied, may stop in the n+-type buffer region. The technique disclosed in Patent Document 2 further forms a second n−-type drift region spaced apart from the first n−-type drift region by the n+-type buffer region. The thickness of the second n−-type drift region is set at a predetermined value.
The below listed Patent Document 3 describes a technique for improving the forward-voltage reverse-recovery-loss tradeoff characteristics of a diode. The diode includes a first semiconductor layer of a first conductivity type having a first major surface and a second major surface, a second semiconductor layer of the first conductivity type formed on the first major surface and doped more heavily than the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed on the second major surface. The impurity concentration and the thickness of the first and third semiconductor layers are selected so that the electric field caused by a depletion layer expanding from the pn-junction between the first and third semiconductor layers may be almost in the first semiconductor layer in the state of sustaining the breakdown voltage and the depletion layer may reach the second semiconductor layer. The cross-sectional area of at least a portion of the first semiconductor layer parallel to the first major surface thereof is reduced toward the second semiconductor layer from the pn-junction between the first and third semiconductor layers.
The below-listed Patent Document 4 describes a technique for improving the forward-voltage reverse-recovery-loss tradeoff characteristics and the soft switching performances of a PIN-diode. The PIN-diode includes a first n-type drift layer and an n-type buffer layer formed in an n-type drift layer. The shortest distance from the pn-junction between a p-type anode layer and the first n-type drift layer to the n-type buffer layer and the width of the n-type buffer layer are set at respective predetermined values so that a certain breakdown voltage may be secured and the tradeoff relationship between the high-speed switching performance with a low switching loss and the soft recovery performance may be improved.
The below-listed Patent Document 5 proposes another technique for improving the tradeoff relationship between the high-speed switching performance with a low switching loss and the soft recovery performance. The semiconductor device disclosed in Patent Document 5 includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first major surface of the first semiconductor layer, the second semiconductor layer being doped more heavily than the first semiconductor layer; and a third semiconductor layer of the first conductivity type formed on the second major surface of the first semiconductor layer, the third semiconductor layer being doped more heavily than the first semiconductor layer. The first semiconductor layer includes at least a portion in which the impurity concentration shows the maximum value. The impurity concentration in the first semiconductor layer reduces gradually toward the second and third semiconductor layers from the portion in which the impurity concentration shows the maximum value.
The below-listed Patent Document 6 proposes a technique for manufacturing a semiconductor device, which exhibits a high-speed switching performance with a low switching loss and a soft switching performance. Oxygen is introduced into an n−-type FZ wafer that constitutes an n−-type first semiconductor layer. Then, a p-type second semiconductor layer and an anode electrode are formed on the FZ wafer. Protons are irradiated onto the FZ wafer from the anode electrode side to introduce crystal defects into the FZ wafer. Then, a heat treatment is performed to make the crystal defects in the FZ wafer recover for setting the net dopant concentration in a portion of the first semiconductor layer to be higher than the initial net dopant concentration in the FZ wafer and for further forming a desired broad buffer structure. The manufacturing method proposed in Patent Document 6 facilitates manufacturing the semiconductor device, which exhibits the preferable switching performances described above, from an FZ bulk wafer with low manufacturing costs, with excellent controllability, and with high throughput of non-defective products.
The patent documents referenced above are as follows:    [Patent Document 1] Published Japanese Translation of PCT International Publication for Patent Application No. 2002-520885    [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2004-193212    [Patent Document 3] Japanese Patent Publication No. 2573736    [Patent Document 4] Japanese Unexamined Patent Application Publication No. 2003-152198    [Patent Document 5] Japanese Unexamined Patent Application Publication No. 2003-318412    [Patent Document 6] International Unexamined Patent Application Publication No. 2007/055352 Pamphlet
For forming a field stop region and such a region doped more heavily than the semiconductor substrate in the semiconductor substrate, it is necessary for the technique described in Patent Document 1 to include a thermal diffusion treatment at a relatively high temperature, higher than 600° C. Especially in manufacturing a device that employs a thin wafer, partings and cracks may be caused in the subsequent metallization step. It is difficult to form only a region doped more heavily than the semiconductor substrate, in the semiconductor substrate. Moreover, the heavily doped region is limited to an n-type region.
According to the technique described in Patent Document 6 for manufacturing a diode, the concentration in the heavily doped region formed in the semiconductor substrate is constant in parallel to the major surface of the semiconductor substrate. In order to form a heavily doped region, the impurity concentration of which changes in parallel to the major surface of the semiconductor substrate, it is necessary to employ a method that includes metal mask alignment, for example, with a relatively low accuracy. By the technique described in Patent Document 6, the heavily doped region formed in the semiconductor substrate is limited to an n-type heavily doped region. The technique described in Patent Document 3, 5 or 6 makes the voltage rise rate (dV/dt) increase as the depletion layer reaches the cathode region or the region doped more heavily than the semiconductor substrate. Therefore, a soft switching performance is not obtained.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a semiconductor device that facilitates improving the relevant tradeoff characteristics and obtaining a soft switching performance. It would be further desirable to provide the method for manufacturing the semiconductor device that facilitates improving the relevant tradeoff characteristics and obtaining a soft switching performance. The invention is applicable to an n-type semiconductor substrate as well as to a p-type semiconductor substrate. The invention is applicable to a semiconductor device that includes a heavily doped region in the semiconductor substrate and to the method for forming such a heavily doped region in the semiconductor substrate independently of the conductivity type of the heavily doped region.